1. Field of the Invention
The invention relates in general to a memory module and writing and reading method thereof, and more particularly to a memory module which can save hardware structure, and writing and reading method thereof.
2. Description of the Related Art
Memory has been applied in data storage for various purposes today. How to ensure that the data stored in the memory is complete is very essential in memory design. Conventionally, an error correction code (ECC) is used to achieve the above requirement. However, owing that the required memory becomes larger, the conventional ECC for detecting and correcting one bit of error, such as a Hamming code, is not satisfying and has been replaced by ECC capable of detecting and correcting multiple bits of error. The ECC used most commonly today is a Reed-Solomon (RS) code.
The RS code is a (N, K) block code. That is, when data of K symbols is inputted, the K-symbol data will be encoded into a codeword with N symbols. The N symbols include a parity code with (2T=N−K) symbols, all the symbols belong to a finite field GF(2m), and each symbol has m bits.
Referring to FIG. 1, a schematic diagram of a conventional memory module is shown. A memory module 100 includes an input buffer 110, a page buffer 120, a RS-code encoder 130 and a memory-cell array 140. The memory module 100 is exemplified to receive a piece of (2m=512)-byte data for illustration in the following description, wherein m=9, but the invention is not limited thereto. The piece of data will be temporarily stored in the input buffer 110 first. If the memory module 100 includes 64 sense amplifiers, the 29-byte data will be temporarily stored in the page buffer 120 in a form of 64 bits at a time. That is, the 29-byte data will be temporarily stored as 64 characters and each character includes 64 bits.
Besides, under consideration of the 29-byte data and additional ECCs, when the RS-code algorithm is performed on the 29-byte data, a field conversion of RS codes is needed. That is, it is necessary to convert from the finite field GF(29) to the finite field GF(210) for the RS-code algorithm. Therefore, the RS-code encoder 130 is corresponding to the finite field GF(210). The RS-code encoder 130 encodes the 29-byte data into 520 symbols according to the RS-code algorithm, wherein each symbol includes 10 bits. The 520 symbols include a parity code with 8 symbols. Then, the parity code is written into the memory-cell array 140 in the form of 64 bits (if the parity code has fewer bits, the empty bit is set to 0) at a time as well as the 64 characters temporarily stored in the page buffer 120.
Referring to FIG. 2, a schematic diagram of another conventional memory module is shown. A memory module 200 includes a memory-cell array 210, a page buffer 220, a RS-code decoder 230, an exclusive or gate 240 and an output buffer 250. If the memory-cell module 200 has 64 sense amplifiers, the memory-cell array 210 outputs 66 characters, which include data of 64 characters and a parity code of 2 characters. Each character includes 64 bits. The 64-character data is temporarily stored in the page buffer 220 and then outputted in the form of 512 bytes to the exclusive or gate 240.
The 66 characters, outputted by the memory-cell array 210, subtract the bits “0” set as being written, and then are transmitted to the RS-code decoder 230 in the form of 522 bytes. Similar to the RS-code encoder 130 of FIG. 1, the RS-code decoder 230 is also corresponding to the finite field GF(210). After the RS-code decoder 230 has received 522 bytes, a 512-byte ECC is obtained according to the RS-code algorithm, and outputted to the exclusive or gate 240. The exclusive or gate performs an exclusive or operation on the corresponding bits of the 512-byte data and the 512-byte ECC to obtain a piece of 512-byte corrected data. The output buffer 250 temporarily stores and outputs the 512-byte corrected data.
The above memory modules 100 and 200 require field conversion of RS codes for converting toward a higher-order field, such as from the finite field GF(29) to the finite field GF(210), during the RS-code algorithm, and thus the used RS-code encoder/decoder requires more inner-circuit components, such as multiplexers or dividers. Consequently, the area of RS-code encoder/decoder and thus the whole hardware cost are increased.